The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
A host device can communicate with a network device via a PCIe bridge. The host device can be, for example, a desktop computer, a laptop computer, or a peripheral device (e.g., a printer). The network device can be, for example, a network interface card or a storage drive. The network device can also be, for example, an Ethernet device, a universal serial bus (USB) device, a serial advanced technology attachment (SATA) device, a small computer system interface (SCSI) device, or other high-speed serial bus device.
The PCIe bridge may include a PCIe interface, a first-in-first-out (FIFO) memory, internal buses, and multiple device interfaces. The PCIe bridge is connected between i) a host control module and/or host memory, and ii) multiple network devices. The FIFO memory is connected between the PCIe interface and the internal busses. The internal busses are connected between the FIFO memory and the device interfaces. Each of the device interfaces is connected to a respective one of the network devices.
The internal buses may include a first bus for high-speed data transfers and a second bus for low-speed data transfers. The FIFO memory is included to handle data transfers between the host memory and the network devices in parallel. Data transfer latency on the internal busses is not fixed, is unpredictable, and is based on a number of parallel executed data transfers, priority levels of the parallel executed data transfers, and size of the FIFO memory.
In operation and during a data transfer from the network devices to the host memory, the network device transfers data and status information associated with the data to the high-speed bus. The data and the status information are then transferred to the PCIe interface via the FIFO memory. The data and the status information are then transferred to the host from the PCIe interface. The data and the status information are written to respective areas of the host memory. The network device then requests an interrupt be sent to the PCIe interface. The PCIe interface then generates and issues the interrupt to an interrupt module of the host device, which may be sent directly from the high-speed bus to the PCIe interface without passing through the FIFO memory.
Due to unpredictable latency of data and status information transfers via the high-speed bus and FIFO memory and the direct transfer of interrupts, the interrupts can bypass corresponding status information. This can cause the host control module, interrupt module, and/or host memory not to have received the corresponding status information when an interrupt is received.